With recent advancements in semiconductor manufacturing technology microelectronic components are becoming smaller and circuitry within such components is becoming increasingly dense. This has led to an increase in wiring levels and a reduction in the wiring pitch to increase the wiring density. Many leading edge processors have multiple levels of high density interconnects.
In order to prepare microelectronic components such as a chip having a high speed, a conductor having a low resistance and a dielectric material having low dielectric constant is used. Typically, microelectronic components employ SiO2 as the interlayer dielectric material having the requisite mechanical and thermal properties.
One challenge is that the low dielectric constant (k) interlayer dielectric strength continues to decline as a result of reduced dielectric constant. Furthermore, the stress transferred to the low K interlayer dielectric continues to increase with lead free conversion and pitch reduction.
Although the following Detailed Description will proceed with reference being made to illustrative embodiments of the claimed subject matter, many alternatives, modifications, and variations thereof will be apparent to those skilled in the art. Accordingly, it is intended that the claimed subject matter be viewed broadly, and be defined only as set forth in the accompanying claims.